1. Background of the Invention
The invention relates generally to stacked microelectronic modules. Specifically, the invention relates to a device comprised of stacked integrated circuit (IC) package layers, such as ball grid array packages (BGA), thin small outline packages, (TSOPS) or connected bare die IC chip layers. The layers may optional include other active or passive electronic components such as surface mounted resistors, capacitors or the like.
The various electronic components in the layers can be connected to an external circuit by means of one or more interposer structures comprising conductive traces on one or more lateral surfaces of the claimed package to define conductive “T-connect” structures which route predetermined circuit signals to predetermined locations.
In the microelectronics industry, there are significant advantages to stacking and interconnecting commercial off the shelf (COTS) integrated circuit packages. The primary advantage of stacking integrated circuits is maximum utilization of limited surface area on a printed circuit board. Vertically stacking integrated circuit packages provides increased circuit density without requiring additional printed circuit board space. Further, stacking integrated circuit packages reduces signal lead lengths between the stacked components, reducing parasitic inductance and capacitance, which in turn, allows the circuits to operate at high clock speeds.
The use of COTS components also provides the advantage of ensuring the stack contains fully burned in, tested and functional die, i.e., ensures the use of known good die (KGD) in the stack.
Industry has recognized the value of stacking COTS integrated circuits as is reflected in U.S. Pat. Nos. 6,028,352 to Eide, 6,806,559 to Gann, and 6,706,971, to Albert, U.S. Pat. No. 6,967,411 to Eide, all to common assignee, Irvine Sensors Corp. and each of which is incorporated fully herein by reference.
The current microelectronic packaging trend is toward ball grid array packages which comprise an array of solder ball interconnections for I/O to and from the internal integrated circuit die on the lower major surface of the BGA package. The solder balls are reflowed to a registered set of conductive pads on an external circuit for interconnection therewith. It is therefore desirable and a need exists to provide a device that optionally takes advantage of the benefits of stacking and that can accommodate ball grid array packages, surface mount, TSOP or other electronic package formats, which device can be adapted for connection with a standard BGA or other user-defined printed circuit board pattern.
2. Brief Summary of the Invention
The present invention is a device comprising a stack of at least two layers, each of which may comprise active and/or passive discrete components, TSOP and/or ball grid array packages, bare integrated circuit die, which layers are stacked and interconnected to define a microelectronic package. The aforementioned electronic devices are collectively, but without limitation, referred to herein as electronic components.
A first layer comprises an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive trace terminates at a lateral edge of the first layer to define an access lead.
A second layer comprises an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive trace terminates at a lateral edge of the second layer to define an access lead.
An interposer structure is disposed between the layers and provides one or more lateral surfaces upon which a layer interconnect trace is defined to create an electrical connection between the respective access leads on each of the layers. The conductive traces on the second layer may readily be electrically connected to an external circuit using a ball grid array pattern, wirebonding or equivalent means.
In the above device, all manner of electronic devices can be efficiently stacked and interconnected in a reliable, low cost microelectronic module.
While the claimed device has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 USC 112, are not to be construed as necessarily limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 USC 112, are to be accorded full statutory equivalents under 35 USC 112.
The invention and its various embodiments can now be better understood by turning to the following detailed description of the preferred embodiments which are presented as illustrated examples of the invention defined in the claims. It is expressly understood that the invention as defined by the claims may be broader than the illustrated embodiments described below.